Magnetic core binary counter



Nov. 6, 1962 R. A. DAVIS ETAL 3,063,038

- MAGNETIC CORE BINARY COUNTER Filed Feb. 9, 1959 2 Sheets-Sheet 1 Nov.6, 1962 R. A. DAVIS ETAL MAGNETIC CORE BINARY COUNTER 2 Sheets-Sheet 2Filed Feb. 9, 1959 3,003,033 Patented Nov. 6, 1962 3,063,038 MAGNETICCORE BINARY COUNTER Roderic A. Davis, Poughkeepsie, and George E. Olson,

Wappingers Falls, N.Y., assignors to International Business MachinesCorporation, New York, N.Y., a

corporation of New York Filed Feb. 9, 1959, Ser. No. 792,194 9 Claims.(Cl. 340-174) This invention relates to logical circuits of the typeuseful in forming binary counters and shift registers and has for anobject the provision of a reliable and novel arrangement of magneticcores and switching devices for performing the counting operations inresponse to a sucsession of input pulses.

A binary trigger circuit may be defined as an elementary storage unit ofa counter which may be placed in either of two stable states. In binaryterminology, it is convenient to refer respectively to afirst state asthe zero state and to the second state as the one state.

While trigger circuits including magnetic cores have heretofore beenutilized, it is an object of the present invention to provide a newcooperative arrangement between an electrical storage device, a magneticcore, and a switching device to form logical circuits including binarycounters of any desired number of stages with but a single input circuitor drive-line connected to the first stage.

It is a further object of the invention to utilize semiconductors as theswitching devices, thereby to provide both amplification andcancellation operations in circuits embodying the present invention.

It is a further object to provide a system of considerable flexibilityincluding both parallel reset and parallel read-out for the cores.

It is a further object to provide logical circuits utilizing a minimumnumber of components and including but a single input circuit to thefirst stage, transistors being utilized for amplification andcancellation purposes in conjunction with magnetic cores driven to oneor the other of two stable states in a predetermined combinatorial code.

In carrying out the present invention in one form thereof, a logicalcircuit such as a binary counter is comprised of a plurality of magneticcores, each in its initial first stable state of magnetization. Inputpulses are applied in succession to the input winding of the first ofsaid cores. An electrical storage device, such as a capac itor, isincluded in the input circuit. Each input pulse as applied to the inputwinding has a polarity tending to produce said first state ofmagnetization. Since the core already has that state, no change iseifected. However, the capacitor is charged and upon termination of theinput pulse, the capacitor discharges to change the magnetization ofsaid first core to its second state. When this occurs, an output isproduced from an output winding. That output has a polarity whichmaintains an associated transistor non-conductive.

Since the first core is now in its second or one state, the next inputpulse will return it to its first or zero state. The resultant outputpulse then has a polarity of direction which turns on the transistor.This transistor, acting as a switching device applies an amplified pulseto an inhibit winding to bias the core to its first state thereby toprevent its operation to its second state upon discharge of thecapacitor.

The input circuit to the second state includes the aforesaid transistor,a resistor, an input winding and a capacitor. Thus as the transistor isturned on, the input winding of the second stage is energized by theamplified pulse but the polarity is in a direction to maintain thesecond core in its first state. Upon discharge of its associatedcapacitor, charged by the amplified pulse, that core is switched to itssecond or one state.

Upon appearance of the third pulse, operations occur identical withthose described above for the first pulse. It may now be observed thatwith the three pulses so far described there will have been producedoperations which produce in the cores, states which in the binary systemmay be taken as representative of 1000, 0100, and 1100. Operationssimilar to the foregoing take place with each succeeding pulse appliedto the single input circuit associated with the first stage. Thus, withbut four cores, sixteen distinctively different combinations may beproduced.

For further objects and advantages of the invention and for details ofcircuitry and operation, reference is to be had to the followingdescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 diagrammatically illustrates one embodiment of the invention;

FIG. 1A is a hysteresis loop ing of the invention; and

FIG. 2 illustrates a further embodiment of the invention.

Referring to FIG. 1, the invention in one form has been shown as appliedto a logical circuit in the form of a binary counter 10 having fourstages ll4. These stages respectively include magnetic elements or cores11-14, each of a material providing substantially rectangular hysteresisloops. As shown in FIG. 1A, each core is capable of assuming one or theother of two different stable remanence conditions Br and -|-Br. Thecore 11 has an input winding 11a, a control winding 11b and an inhibitwinding 11c. Cores 1244 have like windings helpful to an understand-1241-1451, i2b-l4b and IZc-ldc respectively magnetically coupledthereto. Though each winding has been illustrated as including aplurality of turns, it is to be understood that a single conductorthreaded throughout an opening in a magnetic core or otherwisemagnetically coupled thereto is to be deemed a winding, since themagnetic field produced by current flow through astraight conductor canproduce a magnetizing force upon a core of adequate magnitude to changeit from one to the other of its stable states.

The cores 11, i2, 13 and 14 may be made of any of the magnetic materialsheretofore found desirable for magnetic storage devices. For example,they may be made of 470 Mo-Permalloy, each core preferably consisting ofa plurality of laminations, for example, as twenty of them. The inputpulses 15 may be of a magnitude, such as provided with a 45-volt sourcein series with a lO-ohm resistor.

A resistor R and a capacitor C are included in series circuit relationwith input winding 11a. Similarly, one of resistors bi -R and one ofcapacitors C C are respectively connected in series with one of inputwindings liZa-Ma. Each of the latter circuits including input windings12a-14a includes in series therewith one of transistors T T The controlwindings lib-14b are respectively connected to transistor T T to turnthem on and oil. The transistors perform switching functions in theirrespective circuits which also respectively include inhibit windingsTic-14c.

Only one input circuit as at input terminals '16 need be provided forpulses 15 to be counted. The input to logical circuit 10 extends frominput terminals 16 by way of a diode 16d to the junction betweenresistor R and input winding 11a.

Referring now to FIG. 1A, the cores 1144 of FIG. 1 when in one or theother of their stable remanent states, as at B1' and +Br, can be takenas representative of the zero and the one comprising the notations forthe bits used in the binary system.

Assuming now that all cores 11-14 are in their first or zero states asat +Br, FIG. 1A, and that the first of a plurality of the input pulses15 is applied to the input terminals 16, the input winding 11a will beenergized to produce on core 11 a magnetoinotive force in a direction tobias that core to its first state. Since it is already in that state, nochange from one, +Br, to the other, Br, of its magnetization states willocur. While there will be some change in the magnetic flux in core 11,it will be of a relatively low order with a resultant output pulse atcontrol winding 11b of relatively low amplitude and insufiicient to turnon transistor T The input pulses 15, shown as positive-going pulses, areapplied through diode 16a to the upper or positive end of winding 11a.This positive end of winding 11a is so indicated by the heavy black dotadjacent its upper end. Since this same input pulse induces a pulse incontrol winding 1112, a dot is placed adjacent the end which is therebymade positive. Thus the dot on the control winding 11b appears at theupper end of that winding. Thus the dots adjacent one or the other endsof the windings in FIGS. 1 and 2 indicate the disposition of thewindings on each core. Since inhibit winding 110 is to produce magneticforces which act on the core in the same direction as the forcesproduced by Winding 1111, the upper end of winding 11c bears thedot-symbol.

The first of input pulses 15 applied to the circuit including the inputwinding 11a and the capacitor C in one branch, and the resistor R in theother branch, though it does not switch core 11, is effective to chargethe electrical energy storage device shown as capacitor C As soon asthat first input pulse disappears, the capacitor C discharges throughinput winding 11a and resistor R The flow of current through winding11a, in the reverse direction to that produced by the input pulse,develops a magnetizing force on core 11 which changes or switches itfrom its first +Br or zero state to its second --Br or one state. Thusfor the first pulse, cores 11-14 have states corresponding in the binarysystem to 1000.

With the switching of core 11 from its first to its second state, anegative output pulse is developed at the upper end of winding 11b. Thispulse has a polarity which tends to make the base of transistor Tnegative relative to its emitter. Accordingly, transistor T is notturned on, that is, rendered conductive, when core 11 is switched fromits first state to its second state. Moreover, the diode D is connectedin the input circuit to transistor T and poled with a polarity to blockthe negative-going pulses.

With core 11 in its one or -Br state, it will now be assumed that thesecond input pulse is applied to input terminals 16. The resultant flowof current through the winding 11a is in a direction to switch the core11 from its second -Br state to its first state, with a resultantdevelopment at control winding 11b of a positive-going output pulse.This output pulse charges capacitor 11a and makes the base of transistorT positive relative to its emitter. This turns on transistor T with aresultant flow of current from a source shown as battery B. Thus thetransistor T produce an amplified pulse through the inhibit winding liein direction such that the resultant magnetic forces tend to maintaincore 11 in its zero or +Br state.

As transistor T is turned on, the amplified current pulse is alsoapplied to input winding 12a and to the capacitor C of the second stage2. The capacitor C thereby acquires a charge. Similar to the action ofthe first pulse, the flow of current through winding 12a, due to anapplied pulse, is in a direction which biases core 12 to its first orzero state. Thus, there is no change in the magnetic state of core 12when transistor T is turned on though a change occurs when transistor Tis turned olf.

Returning now to stage ll, upon disappearance upon winding 11a of thesecond pulse, capacitor C again discharges through winding 11a with thedevelopment upon winding 13a is in a direction to bias it core 11 of amagnetizing force again tending to switch it from its first +131- stateto its second -Br state. The core 11, however, remains in its firststate due to the magnetic bias on that core resulting from theenergization of inhibit winding 110. This result is achieved by reasonof the charge acquired by capacitor lie when transistor T was turned on.That charge on capacitor He maintains transistor T conductive duringdischarge of capacitor C Thus the core 11 is not switched by thedischarge of capacitor C following the disappearance of the pulse whichturned on transistor T. The time constants of the discharge circuits forcapacitors C and 11a through their associated resistors R and llr are ofthe same order, preterably equal, to assure the foregoing operation. Inthis connection, the resistor 11r may be omitted with an appropriatechange in the size of capacitor 11a to provide the desired time constantfor its discharge circuit through transistor T and resistor R Theresistor 11;- is shown to illustrate the manner in which the amplifiedimpulse from control winding 11b may be attenuated to a desired value inthe event the change in flux cutting winding 11b produces a pulse ofundesired large amplitude. A reduction in amplitude of the output pulsefrom control winding 11b may be attained by reducing the cross-sectionof core 11 or where winding 11b comprises more than a single conductor,by reducing its number of turns or magnetic coupling with core 11.

By reason of capacitor He, the transistor T remains conductive for aperiod corresponding with that requ1red for the discharge of capacitor CAfter discharge of capacitor C transistor T by reason of thedisappearance of the charge on capacitor 111:, is turned ofi. The d odeD blocks discharge of capacitor 11c through control winding 11b toassure the above-described operation.

When transistor T is turned off, the capacitor C discharges throughwinding 12a and resistor R with the resultant development on core 12 ofa magnetomotive force of magnitude adequate to switch core 12 from itsfirst +Br, or zero state to its second -Br or one state. Thus for thesecond pulse, the cores in the binary system are representative of 0100.

The system is now in condition for the application of the third pulse.That third pulse produces the same operations as the first pulse sincecore 11 was, by the second pulse, returned to its first +Br, or zerostate. Accordingly, after discharge of capacitor C as a result of thethird pulse, the core 11 is again switched to its second Br or onestate. Accordingly, the states of magnetization of the cores l1-14 thenrepresent in the binary system 1100.

With cores 11 and 12 in their second -Br, or one states, the fourthpulse is effective first to switch core 11 to its +Br, or zero, state.The output from control winding 11b turns on transistor T which againfunctions to prevent a change of state of core 11 upon later dischargeof capacitor C The output from transistor T is applied through inputWinding 12a to switch core 12 from its -Br or one state to its +Br orzero state. This develops from control Winding 12b an output which isapplied to transistor T to turn it On. Capacitor 12a is at that timecharged. With transistor T turned on, the inhibit winding 12c isenergized and so is the input circuit to the third stage including core13. The flow of current through to its first state. That current alsocharges capacitor C When transistor T is turned off as a result oftermination of the fourth pulse, capacitor C discharges to switch core13 to its one or -Er state. Thus for the fourth pulse, the cores 11-14in the binary system have magnetic states representative in the binarysystem of 0010.

The foregoing operations are repetitious in character. Thus the fifthpulse functions in a manner identical to the first pulse to switch core11 to its one state, while the sixth pulse functions in the same manneras the secnd pulse to return core 11 at its zero state and to switchcore 12 to its one state. The seventh pulse, like the first pulse,switches core 11 to its one state. Thus for the fifth, sixth and seventhpulses, the magnetic states of the cores 11-14 are respectivelyrepresentative of 1010, 0110 and 1110.

Upon appearance of the eighth pulse, the cores 11, 12 and 13 areswitched to their zero states in the same manner as occurred uponapplication of the fourth pulse, and the core 14- is switched to its onestate. The operations above described are again repeated. The sequenceas a whole has been represented in Table I for the four cores and forthe application of sixteen pulses.

Table I Cores Pulse No. 11 12 13 14 0 0 0 0 0 .1 1 O 0 0 2 -1 0 1 0 0 31 1 O 0 4 O 0 1 0 5 1 0 1 0 6 O 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1 10 01 0 1 11 1 1 0 1 '12 O 0 1 1 13. 1 0 1 1 14 0 1 1 1 15 1 1 1 1 16 0 O Oi 0 Upon the appearance of the sixteenth pulse itfwill be noted that allof cores 11-14 are switched fromi their Br or one states to their +Br orzero states. Since core 14 for the sixteenth pulse is for the first timeswitched from its Br or one state to its +Br or zero state, an outputfrom stage 4 corresponding with the foregoing change in magnetizationstate will be indicative of the completed count of sixteen by the fourstages of FIG. 1. Accordingly, there is provided on core 14 an outputwinding 14d, with a dot-symbol at its upper end, which winding producesan output pulse for an output circuit including a diode 18. The diode 18prevents appearance at output terminals 19 of a pulse developed onoutput winding 14d upon switching of core 14 from its zero to its onestate, as occurred upon application of the eighth pulse, but passes tothe output terminals 19 the output pulse developed by the change ofstates occurring only upon application of the sixteenth pulse.

It will be understood that the output circuit from terminals 19 may beutiiized to energize a second counter and may also be used for othertypes of utilization circuits as will be understood by those skilled inthe art.

Though transistors of the PNP type may be utilized with correspondingchanges in polarity of the sources, and though the values or" thecircuit components are not critical and may be changed materiallywithout sacrifice of performance of the system as a whole, a typical setof values for the circuit components has been given in the followingtable which is to be taken as exemplary of values found useful in atypical embodiment of the invention:

Table II C -C :.01 microfarad R ,-R ,=10,00O ohms C -C :.0()1rnicrofarad Source B=l8 volts T -T :NPN alloy junction type Cores11-14:Sprague type 31Zl8 Features of the system of FIGS. 1 and 2 may beutilized in/ or omitted from embodiments of the invention.

'the cores 11-14. If that pulse from its one to its zero state.

6 For example, mention has been made of the omission of resistors11r-14r from FIG. 1. These resistors do not appear in the system of FIG.2. To safeguard operation against noise each transistor may include asource of bias voltage in its input circuit of polarity biasing thetransistor to its non-conductive state. Such sources, of one-half voltmagnitude, have been shown in FIG. 2 as bias batteries B1-B4. As wellunderstood by those skilled in the art, either the +Br state or the -Brstate may be taken to be representative of zero in the binary system andthe other state to be representative of one. Simila ly the input andoutput circuits of the transistors may be conventional. Thus the inputcircuit may extend between the collector and base instead of between thecollector and emitter, as shown in FIGS. 1 and 2. The diodes D -D asexplained above, and diode 16d isolate the charging circuits of therespective capacitors C -C from their discharge circuits. Similarisolation or polarity discrimination is provided by the correspondingdiodes of FIG. 2.

Referring now to FIG. 2, the system of FIG. 1 has been shown with outputwindings 11d-14d respectively associated with the cores 11-14. Alsocoupled to the respective cores 11-14 are reset and read-out windings11g-14g. With the addition of an output winding for each core, ou'putcircuits may be connected to each stage as by output terminals 21-24.Included in the respective output circuits are diodes 11f-14f poled orconnected to provide output pulses whenever a core is changed from itszero state to its one state. Thus the diodes prevent passage of pulseswhen the top of each winding is negative, as in switching from a one toa zero state. Thus the dot-symbols appear at the lower end of windings11d-14d.

The additional windings are to be taken as exemplary of the flexibilityof the present invention in its application to circuits of varioustypes. By means of the windings 11g-14g, additional operations arereadily provided. A pulse of short duration applied as from a source Bthrough a high-speed switching device, but for simplicity shown as aconventional switch 26, will be simultaneously effective upon all of beof polarity to switch to its zero state each core then in its one state,the result Will be the switching from its zero to its one state eachcore following the one switched by said pulse In this manner the ones"are transferred from one stage to the next, thus meeting therequirements of a shifting register. The applied pulse from source Bwill be positive-going with the windings having the indicateddisposition or direction of turns on the cores.

As an example of the foregoing operations, it will be assumed that cores12 and 14 are in their zero states and that cores 11 and 13 are in theirone states. A pulse now applied to windings 11g and 14g will producemagnetic forces on cores 11 and 13 in directions to switch them to theirzero states. Like forces are applied to cores 12 and 14 but since theyare already in their zero states +Br, FIG. 1A, no change of stateoccurs. The cores 11 and 13 are switched to their zero states however.When so changing their states from Br to +Br, FIG. 1A, windings 11b and13b turn on transistors T and T The inhibit windings 11c and are therebyenergized and capacitors C and C are charged. As the applied pulsedisappears these capacitors are eifective, as above described, to switchcores 12 and 14 to their one states. In this manner, the ones have eachbeen advanced a stage.

Besides the shift-register operation, parallel read-out with reset isachieved by applying from source B 21 pulse of longer duration. As anexample, it will again be assumed that cores 12 and 14 are in their zerostate and that cores 11 and 13 are in their 1 state. The pulse of longerduration will reset cores 11 and 13 to their zero states Withoutswitching by operation of the energy storing devices or capacitors C andC of cores 12 and 14 since each storage device or capacitor uponreceiving a charge, due to the change in flux in the cores 1144, beginsto lose that charge through its discharge circuit as soon as steadystate conditions obtain. Accordingly, the reset impulses will have aduration suificiently long to permit capacitors C -C to discharge theiracquired charges to values below those effective to switch the cores 12and 14 from their zero" states to their one states.

With the above understanding of the invention it will be understood thatmany further variations may be made for adaptation in logic circuits ofmany kinds, and that certain features may be used without otherfeatures, all within the scope of the appended claims. For example,additional output windings like winding 14d of FIG. 1 may be providedfor each of the cores of the embodiment of FIG. 2 together with diodesso that an output from each core will be obtained when switched from aone states to a zero state. Simi'arly, the cores of FIG. 1 may beprovided with output windings 11d-14d and diodes 11f-14f poled likethose of FIG. 2 for production of an output pulse each time a core isswitched from a zero state to a one state. Obviously all cores may haveone or more output windings of each type and in number as may be neededto meet the requirements of particular logic systems.

While there have been shown and described and pointed out thefundamental novel features of the invention as applied to a preferredembodiment, it will be understood that various omissions andsubstitutions and changes in the form and details of the deviceillustrated and in its operation may be made by those skilled in the artwithout departing from the spirit of the invention. It is the intention,therefore, to be limited only as indicated by the scope of the followingclaims.

What is claimed is:

1. A logical circuit comprising a plurality of magnetic elements eachhaving two stable magnetic states, separate input and control windingsmagnetically coupled to each said element,

means including an electrical energy storage device connected in seriescircuit relation with each said input winding,

means including for each said storage device in sociated input winding,

means including an input circuit for applying to a first of said inputwindings input pulses acting in direction to switch said element from asecond to a first of said stable states and to charge said storagedevice, said storage device discharging through said discharge circuitupon disappearance of said input pulse for producing a current flowthrough said input winding in a direction to develop a magnetizing forceto change said element from one to the other of its two stable states,

isolating means connected between each said discharge circuit and eachsaid input circuit for preventing flow of current from each said storagedevice to each input circuit,

means including a transistor for each said element, each said transistorhaving an input circuit including a control Winding of its associatedelement and having an output circuit including at least the inputwinding of another of said elements, each said input circuit to saidtransistors having connected therewith energy storing means forregulating the timeduration of a control signal applied to that inputcircuit, and

output means including an output winding magnetically coupled to atleast one of said elements for developing an output signal when itselement is switched from one to the other of its two stable states.

a resistor forming a discharge circuit series with its as- 2. Thelogical circuit of claim 1 in which for each said magnetic element saidenergy storing means includes a discharge circuit having a time constantof the same order of magnitude as the time constant of said dischargecircuit of the associated storage device.

3. The logical circuit of claim 2 in which each said discharge circuitof said energy storing means includes a resistor connected between saidenergy storing means and the associated transistor and in which eachsaid input circuit to said transistors has connected therewith a diodefor blocking pulses produced when its magnetic element is switched fromits first to its second state and for blocking discharge of said energystoring means through its associated control wind- 4. A logical circuitcomprising a magnetic element having a first and a second stableremanent magnetic state,

separate input, control and inhibit windings magnetically coupled tosaid element,

input means including an input circuit for said input winding forapplying input pulses thereto, each said input pulse being in adirection to develop by said input winding a magnetizing force tendingto change said element to its first state from its second state,

said input circuit including an electrical storage device for receivingelectrical energy from each said input pulse and in giving up the storedenergy upon termination of said input pulse producing current flowthrough said input winding in a direction to develop a magnetizing forcetending to change said element to its second state from its first state,

a transistor in circuit with said inhibit winding for controlling theenergization thereof to produce thereby a magnetizing force on saidelement in a direction to prevent change of said element from its firstto its second state, and

a control circuit for said transistor including said control winding,said transistor being rendered conductive by said control winding uponchange of state of said element to its first state from its second statefor energization of said inhibit winding thereby to prevent said elementfrom changing from its first to its second state upon discharge of saidelectrical storage device,

said control circuit including a capacitor for maintaining saidtransistor conductive for a time interval at least as great as the timerequired for discharge of said energy of said electrical storage device.

5. The logical circuit of claim 4 in which there is provided a diodeconnected between said transistor and said control winding and poled toblock discharge of said capacitor through said control winding.

6. The logical circuit of claim 4 in which there is provided a dischargecircuit for said electrical storage device including said input windingand excluding said input means.

7. The logical circuit of claim 4 in which there are provided aplurality of like magnetic elements and associated windings andcircuits, the transistor associated with each said element including aconnection to the input winding of a succeeding element for applying aninput pulse thereto each time said switching device producesenergization of its associated inhibit winding, whereby said magneticelements are successively switched between their first and secondmagnetic states as said input pulses are sequentially applied to theinput winding associated with a first of said elements.

8. The logical circuit of claim 4 in which said control circuit includesattenuating means to assure that said transistor is not renderedconductive by the output of said control winding upon application tosaid input winding of a pulse tending to change said element to itsfirst state from its second state during the time said element alreadyis in its first state.

9 9. The logical circuit of claim 7 in which said attenuating meanscomprises a diode and a resistor in series circuit relation.

References Cited in the file of this patent UNITED STATES PATENTS 10 LoDec. 23, 1958 Ostroif Sept. 1, 1959 Jones Nov. 3, 1959 Moore Mar. 22,1960 Kihn et a1. Oct. 4, 1960 Eckert Jan. 31, 196 1 Hofiman et a1 July4, 1961 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No3,,063 038 November 6 1962 Roderic A. Davis et a1o It is herebycertified that error appears in the above numbered patent requiringcorrection and that the said Letters Patent should read as correctedbelow.

Column 9, line l for the claim reference numeral "7" read 8 e Signed andsealed this 14th day of May 1963a (SEAL) Attestz DAVID L. LADD ERNEST W.SWIDER Commissioner of Patents Attesting Officer

